DS580 Datasheet, PDF (31/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
PHY_rx_er
The PHY drives the Receive Error signal (PHY_rx_er) synchronously to PHY_rx_clk. The PHY drives PHY_rx_er
for one or more PHY_rx_clk periods to indicate that an error (e.g., a coding error, or any error that the PHY is capa-
ble of detecting) was detected somewhere in the frame presently being transferred from the PHY to the Ethernet
Lite MAC.
PHY_rx_er should have no effect on the Ethernet Lite MAC while PHY_dv is de-asserted. This signal is transferred
between the PHY_rx_clk and processor clock domains at the asynchronous RX bus FIFO interface.
The PHY will provide a minimum of 10 nS setup and hold time for this signal in reference to PHY_rx_clk. Figure 22
shows the behavior of PHY_rx_er during frame reception with errors.
X-Ref Target - Figure 22
PHY_rx_clk
PHY_dv
PHY_rx_er
PHY_rx_data[3:0] ^{preamble SFD D0 D1 xx D3}
CRC
Figure 22: Receive With Errors
DS580_22_041910
Table 15 shows the possible combinations for the receive signals.
Table 15: Possible Values for PHY_dv, PHY_rx_er, and PHY_rx_data[3:0]
PHY_dv
PHY_rx_er
PHY_rx_data[3:0]
Indication
0
0
0000 through 1111
Normal inter-frame
0
1
0000
Normal inter-frame
0
1
0001 through 1101
Reserved
0
1
1110
False carrier indication
0
1
1111
Reserved
1
0
0000 through 1111
Normal data reception
1
1
0000 through 1111
Data reception with errors
PHY_crs
The PHY drives the Carrier Sense signal (PHY_crs) active to indicate that either the transmit or receive is non-idle
when operating in half duplex mode. PHY_crs is de-asserted when both the transmit and receive are idle.
The PHY drives PHY_crs asserted throughout the duration of a collision condition. PHY_crs is not synchronous to
either the PHY_tx_clk or the PHY_rx_clk. The PHY_crs signal is not used in full duplex mode. The PHY_crs signal
is used by both the Ethernet Lite MAC transmit and receive circuitry and is double synchronized to the processor
clock as it enters the Ethernet Lite MAC.
DS580 September 21, 2010
www.xilinx.com
31
Product Specification