DS580 Datasheet, PDF (38/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
The XPS Ethernet Lite MAC resource utilization for various parameter combinations measured with Spartan-6 as
the target device are detailed in Table 20.
Table 20: Ethernet Lite MAC Performance and Resource Utilization for the Spartan-6 FPGA
(Device: xc6slx45t-fgg484-2)
Parameter Values
Device Resources
Performance
Slices
Slice
Flip-Flops
LUTs
Block
RAMS
F_Max
(MHz)
0
0
0
0
0
0
352
589
719
2
110
1
0
0
0
0
0
336
531
641
2
110
1
1
1
0
0
0
345
556
698
4
110
1
1
1
0
1
0
364
615
747
4
110
1
0
0
0
1
0
338
590
686
2
110
1
1
1
1
0
0
403
642
852
4
110
1
1
1
1
1
0
408
701
883
4
110
1
0
0
1
0
0
382
841
953
2
110
System Performance
To measure the system performance (F_MAX) of this core, it was added to a Virtex-4 FPGA system, a Virtex-5 FPGA
system, a Spartan-3ADSP FPGA system, a Virtex-6 FPGA system, and a Spartan-6 FPGA system as the Device
Under Test (DUT) as shown in Figure 25, Figure 26, Figure 27, Figure 28 and Figure 29.
Because the XPS Ethernet Lite MAC core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When this core is combined with other designs in the
system, the utilization of FPGA resources and timing of the design will vary from the results reported here.
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DS580 September 21, 2010
Product Specification