DS892 Datasheet, PDF (74/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 86: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
0.90V
Units
-3
-2
-1 -1L -1L
BPI Master Flash Mode Programming Switching
T_BPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
10
10
10
10
10
ns, Max
T_BPIDCC/T_BPICCD
D[15:00] setup/hold
SPI Master Flash Mode Programming Switching
3.5/0 3.5/0 3.5/0 3.5/0 3.5/0 ns, Min
T_SPIDCC/T_SPICCD
D[03:00] setup/hold
T_SPIDCC/T_SPICCD
D[07:04] setup/hold
T_SPICCM
MOSI clock to out
T_SPICCFC
FCS_B clock to out
DNA Port Switching
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
3.0/0
3.5/0
8.0
8.0
ns, Min
ns, Min
ns, Max
ns, Max
F_DNACK
DNA port frequency
STARTUPE3 Ports
200 200 200 200 200 MHz, Max
T_USRCCLKO
STARTUPE3 USRCCLKO input port to CCLK
pin output delay
1.00/
6.00
1.00/
6.70
1.00/
7.50
1.00/
7.50
1.00/
7.50
ns, Min/Max
T_DO
DO[3:0] ports to D03-D00 pins output delay
1.00/
6.70
1.00/
7.70
1.00/
8.40
1.00/
8.40
1.00/
8.40
ns, Min/Max
T_DTS
DTS[3:0] ports to D03-D00 pins 3-state
delays
1.00/
7.30
1.00/
8.30
1.00/
9.00
1.00/
9.00
1.00/
9.00
ns, Min/Max
T_FCSBO
FCSBO port to FCS_B pin output delay
1.00/
6.90
1.00/
8.00
1.00/
8.60
1.00/
8.60
1.00/
8.60
ns, Min/Max
T_FCSBTS
FCSBTS port to FCS_B pin 3-state delay
1.00/
6.90
1.00/
8.00
1.00/
8.60
1.00/
8.60
1.00/
8.60
ns, Min/Max
T_USRDONEO
USRDONEO port to DONE pin output delay
1.00/
8.50
1.00/
9.60
1.00/
10.40
1.00/
10.40
1.00/
10.40
ns, Min/Max
T_USRDONETS
USRDONETS port to DONE pin 3-state delay
1.00/
8.50
1.00/
9.60
1.00/
10.40
1.00/
10.40
1.00/
10.40
ns, Min/Max
T_DI
D03-D00 pins to DI[3:0] ports input delay
0.5/
2.6
0.5/
3.1
0.5/
3.5
0.5/
3.5
0.5/
3.5
ns, Min/Max
F_CFGMCLK
F_CFGMCLKTOL
STARTUPE3 CFGMCLK output frequency
STARTUPE3 CFGMCLK output frequency
tolerance
50
±15
50
±15
50
±15
50
±15
50
±15
MHz, Typ
%, Max
Startup Timing
T_{DCI_MATCH}
Specifies a stall in the startup cycle until the
digitally controlled impedance (DCI) match
4
4
4
4
4
ms, Max
signals are asserted.
Notes:
1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this
duty-cycle requirement.
DS892 (v1.12) April 1, 2016
Product Specification
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