DS892 Datasheet, PDF (60/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 68: GTY Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
Min
F_GCLK
T_RCLK
T_FCLK
T_DCREF
Reference clock frequency range
60
Reference clock rise time
20% – 80%
–
Reference clock fall time
80% – 20%
–
Reference clock duty cycle
Transceiver PLL only
40
Typ
–
200
200
50
X-Ref Target - Figure 8
80%
T_RCLK
Max
820
–
–
60
Units
MHz
ps
ps
%
20%
T_FCLK
ds892_05_120414
Figure 8: Reference Clock Timing Parameters
Table 69: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask⁽¹⁾
Symbol
Description
Offset
Frequency
Min
Typ
Max
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–112
phase noise mask at
100 kHz
–
–
–128
REFCLK frequency = 156.25 MHz.
1 MHz
–
–
–145
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–103
QPLL_REFCLKMASK
phase noise mask at
REFCLK frequency = 312.5 MHz.
100 kHz
–
–
–123
1 MHz
–
–
–143
QPLL0/QPLL1 reference clock select
10 kHz
–
–
–98
phase noise mask at
100 kHz
–
–
–117
REFCLK frequency =625 MHz.
1 MHz
–
–
–140
10 kHz
–
–
–112
CPLL reference clock select phase noise _{100 kHz}
–
–
–128
mask at REFCLK
frequency = 156.25 MHz.
1 MHz
–
–
–145
50 MHz
–
–
–145
10 kHz
–
–
–103
CPLL_REFCLKMASK
CPLL reference clock select phase noise ^{100 kHz}
mask at REFCLK frequency = 312.5 MHz. _{1 MHz}
–
–
–
–123
–
–143
50 MHz
–
–
–145
10 kHz
–
–
–98
CPLL reference clock select phase noise ^{100 kHz}
–
–
–117
mask at REFCLK frequency = 625 MHz. _{1 MHz}
–
–
–140
50 MHz
–
–
–144
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes:
1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
DS892 (v1.12) April 1, 2016
Product Specification
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