DS892 Datasheet, PDF (23/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
• T_{OUTBUF_DELAY_TD_PAD} is the delay from the T pin to the IOB pad through the output buffer of an IOB
pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output
buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than
T_{OUTBUF_DELAY_TD_PAD} when the DCITERMDISABLE pin is used. In HR I/O banks, the on-die termination
turn-on time is always faster than T_{OUTBUF_DELAY_TD_PAD} when the INTERMDISABLE pin is used.
Table 27: IOB High Range (HR) Switching Characteristics
I/O Standards
T_{INBUF_DELAY_PAD_I}
1.0V
0.95V
0.9V
-3
-2
-1/
-1L
-1L
T_{OUTBUF_DELAY_O_PAD}
1.0V
0.95V
0.9V
-3
-2
-1/
-1L
-1L
T_{OUTBUF_DELAY_TD_PAD}
1.0V
0.95V
0.9V
-3
-2
-1/
-1L
-1L
Units
BLVDS_25
0.46 0.58 0.64 0.64 1.37 1.37 1.62 1.62 1.39 1.40 1.66 1.66 ns
DIFF_HSTL_I_18_F 0.42 0.53 0.57 0.57 0.71 0.71 0.90 0.91 0.82 0.82 1.06 1.06 ns
DIFF_HSTL_I_18_S 0.42 0.53 0.57 0.57 0.83 0.83 1.02 1.03 0.93 0.94 1.16 1.16 ns
DIFF_HSTL_I_F
0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.93 0.90 0.90 1.14 1.14 ns
DIFF_HSTL_I_S
0.42 0.53 0.57 0.57 0.77 0.77 0.96 0.96 0.95 0.98 1.23 1.23 ns
DIFF_HSTL_II_18_F 0.42 0.53 0.57 0.57 0.80 0.80 0.99 1.00 0.95 0.98 1.23 1.23 ns
DIFF_HSTL_II_18_S 0.42 0.53 0.57 0.57 0.83 0.83 1.03 1.03 1.01 1.03 1.28 1.28 ns
DIFF_HSTL_II_F
0.42 0.53 0.57 0.57 0.71 0.71 0.91 0.91 0.87 0.87 1.11 1.11 ns
DIFF_HSTL_II_S
0.42 0.53 0.57 0.57 0.80 0.80 0.99 0.99 0.95 0.96 1.20 1.20 ns
DIFF_HSUL_12_F
0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.92 0.73 0.73 0.92 0.92 ns
DIFF_HSUL_12_S
0.42 0.53 0.57 0.57 0.82 0.82 1.01 1.02 0.82 0.82 1.01 1.02 ns
DIFF_SSTL12_F
0.42 0.53 0.57 0.57 0.70 0.70 0.89 0.89 0.81 0.81 1.02 1.02 ns
DIFF_SSTL12_S
0.42 0.53 0.57 0.57 1.04 1.04 1.26 1.26 1.04 1.04 1.26 1.26 ns
DIFF_SSTL135_F
0.42 0.53 0.57 0.57 0.70 0.70 0.88 0.88 0.86 0.87 1.09 1.09 ns
DIFF_SSTL135_S
0.42 0.53 0.57 0.57 0.77 0.77 0.96 0.96 0.93 0.94 1.18 1.18 ns
DIFF_SSTL135_R_F 0.42 0.53 0.57 0.57 0.72 0.72 0.91 0.91 0.83 0.84 1.06 1.06 ns
DIFF_SSTL135_R_S 0.42 0.53 0.57 0.57 0.80 0.80 1.00 1.00 0.93 0.93 1.17 1.17 ns
DIFF_SSTL15_F
0.42 0.53 0.57 0.57 0.66 0.66 0.85 0.85 0.81 0.82 1.05 1.05 ns
DIFF_SSTL15_S
0.42 0.53 0.57 0.57 0.78 0.78 0.98 0.98 0.96 0.96 1.20 1.21 ns
DIFF_SSTL15_R_F 0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.92 0.86 0.86 1.09 1.09 ns
DIFF_SSTL15_R_S 0.42 0.53 0.57 0.57 0.81 0.81 1.01 1.02 0.93 0.94 1.18 1.18 ns
DIFF_SSTL18_I_F 0.42 0.53 0.57 0.57 0.74 0.74 0.94 0.94 0.92 0.93 1.18 1.19 ns
DIFF_SSTL18_I_S 0.42 0.53 0.57 0.57 0.86 0.86 1.05 1.06 0.86 0.86 1.05 1.06 ns
DIFF_SSTL18_II_F 0.42 0.53 0.57 0.57 0.71 0.71 0.90 0.90 0.87 0.88 1.11 1.12 ns
DIFF_SSTL18_II_S 0.42 0.53 0.57 0.57 0.83 0.83 1.03 1.03 0.99 1.04 1.29 1.30 ns
HSTL_I_18_F
0.52 0.55 0.59 0.59 0.73 0.73 0.93 0.93 0.84 0.84 1.08 1.08 ns
HSTL_I_18_S
0.52 0.55 0.59 0.59 0.85 0.85 1.05 1.05 0.95 0.96 1.18 1.18 ns
HSTL_I_F
0.52 0.55 0.59 0.59 0.75 0.75 0.94 0.95 0.92 0.92 1.16 1.17 ns
HSTL_I_S
0.52 0.55 0.59 0.59 0.79 0.79 0.98 0.99 0.97 1.00 1.25 1.25 ns
HSTL_II_18_F
0.52 0.55 0.59 0.59 0.82 0.82 1.01 1.02 0.97 1.00 1.25 1.25 ns
HSTL_II_18_S
0.52 0.55 0.59 0.59 0.85 0.85 1.05 1.05 1.03 1.05 1.30 1.30 ns
HSTL_II_F
0.52 0.55 0.59 0.59 0.73 0.73 0.93 0.93 0.89 0.90 1.13 1.13 ns
HSTL_II_S
0.52 0.55 0.59 0.59 0.82 0.82 1.01 1.02 0.98 0.98 1.22 1.22 ns
DS892 (v1.12) April 1, 2016
Product Specification
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