DS892 Datasheet, PDF (35/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 31: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard Attribute
SUB_LVDS
TMDS_33
SUB_LVDS
TMDS_33
Notes:
1. C_REF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
R_REF
(Ω)
100
50
C_REF(1)
(pF)
0
0
V_MEAS
(V)
0⁽²⁾
0⁽²⁾
V_REF
(V)
0
3.3
Block RAM and FIFO Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics
Symbol
Description
Maximum Frequency
F_{MAX_WF_NC}
Block RAM
(Write First and No Change modes)
F_{MAX_RF}
F_{MAX_FIFO}
Block RAM (Read First mode)
FIFO in all modes without ECC
Block RAM and FIFO in ECC configuration
without PIPELINE
F_{MAX_ECC}
Block RAM and FIFO in ECC configuration
with PIPELINE and Block RAM in Write First
or No Change mode.
Block RAM in ECC configuration in
Read First mode with PIPELINE
F_{MAX_ADDREN_RDADDRCHANGE}
Block RAM with address enable and read
address change compare turned on.
T_{PW_WF_NC(1)}
Block RAM in WRITE_FIRST and
NO_CHANGE modes and FIFO.
Clock High/Low pulse width
T_{PW_RF(1)}
Block RAM in READ_FIRST modes.
Clock High/Low pulse width
Block RAM and FIFO Clock-to-Out Delays
T_{RCKO_DO}
Clock CLK to DOUT output (without output
register)
T_{RCKO_DO_REG}
Clock CLK to DOUT output (with output
register)
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V
-3
-2 -1/-1L -1L
Units
660
585
525
525
MHz
575
510
460
400
MHz
660
585
525
525
MHz
530
450
390
390
MHz
660
585
525
525
MHz
575
510
460
400
MHz
575
510
460
400
MHz
758
855
952
952 ps, Min
870
980 1087 1250 ps, Min
1.13 1.44 1.64
0.37 0.44 0.49
1.64
0.49
ns,
Max
ns,
Max
Notes:
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse width requirements at the higher
frequencies.
DS892 (v1.12) April 1, 2016
Product Specification
www.xilinx.com
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