DS892 Datasheet, PDF (54/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
GTH Transceiver Protocol Jitter Characteristics
For Table 58 through Table 63, the UltraScale Architecture GTH Transceiver User Guide (UG576) contains
recommended settings for optimal usage of protocol specific characteristics.
Table 58: Gigabit Ethernet Protocol Characteristics (GTH Transceivers)
Description
Line Rate (Mb/s)
Min
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
–
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
0.749
Max
0.24
–
Units
UI
UI
Table 59: XAUI Protocol Characteristics (GTH Transceivers)
Description
Line Rate (Mb/s)
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
3125
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
Min
–
0.65
Max
0.35
–
Units
UI
UI
Table 60: PCI Express Protocol Characteristics (GTH Transceivers)⁽¹⁾
Standard
Description
Condition
Line Rate (Mb/s)
PCI Express Transmitter Jitter Generation
PCI Express Gen 1 Total transmitter jitter
2500
PCI Express Gen 2 Total transmitter jitter
5000
PCI Express Gen 3^{(2) Total transmitter jitter uncorrelated}
Deterministic transmitter jitter uncorrelated
8000
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1 Total receiver jitter tolerance
2500
PCI Express Gen 2^{(2) Receiver inherent timing error}
Receiver inherent deterministic timing error
5000
PCI Express Gen 3⁽²⁾
Receiver sinusoidal
jitter tolerance
0.03 MHz–1.0 MHz
1.0 MHz–10 MHz
10 MHz–100 MHz
8000
Min
–
–
–
–
0.65
0.40
0.30
1.00
Note 3
0.10
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
Max Units
0.25
UI
0.25
UI
31.25
ps
12
ps
–
UI
–
UI
–
UI
–
UI
–
UI
–
UI
DS892 (v1.12) April 1, 2016
Product Specification
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