DS892 Datasheet, PDF (22/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 26: Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and Package
Memory
Standard
I/O
Bank
Type
Package
DRAM Type
Speed Grade, Temperature Ranges,
and V_CCINT Operating Voltages
1.0V
0.95V
0.90V
-3E
-2E
-2I
-1C/I
/LI
-1L
Units
DDR3L
Single rank
All FF packages ^component
All FL packages _{1 rank DIMM(1)(2)}
FBVA676
FBVA900
2 rank DIMM⁽¹⁾⁽³⁾
4 rank DIMM⁽¹⁾⁽⁴⁾
HP
Single rank
component
1866
1600
1333
800
1600
1866
1600
1333
800
1600
1866
1600
1333
800
1600
1600
1333
1066
606
1600
1600
1333
1066
606
1600
Mb/s
SFVA784
1 rank DIMM⁽¹⁾⁽²⁾
2 rank DIMM⁽¹⁾⁽³⁾
1333
1066
1333
1066
1333
1066
1333
1066
1333
1066
4 rank DIMM⁽¹⁾⁽⁴⁾
606
606
606
606
606
HR
All
Single rank
component
1066 1066 1066 800
800
QDR II+⁽⁶⁾
All
All
Single rank
component
633
600
600
550
550
QDRIV-XP
RLDRAM III
HP
All
Single rank
component
All FF packages
All FL packages
HP
FBVA676
FBVA900
Single rank
component
800
800
800
667
1066 1066 1066 933
667
MHz
933
SFVA784
933
933
933
800
800
HP
LPDDR3
HR
All
Single rank
component
All
Single rank
component
1600
1066
1600
1066
1600
1066
1600
1066
1600
1066
Mb/s
Notes:
1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
3. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
4. Includes: 2 rank 2 slot, 4 rank 1 slot.
5. Memory device must be rated at 1600 or above.
6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.
IOB Pad Input, Output, and 3-State
Table 27 (high-range IOB (HR)) and Table 28 (high-performance IOB (HP)) summarizes the values of
standard-specific data input delay adjustments, output delays terminating at pads (based on standard)
and 3-state delays.
• T_{INBUF_DELAY_PAD_I} is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The
delay varies depending on the capability of the SelectIO input buffer.
• T_{OUTBUF_DELAY_O_PAD} is the delay from the O pin to the IOB pad through the output buffer of an IOB
pad. The delay varies depending on the capability of the SelectIO output buffer.
DS892 (v1.12) April 1, 2016
Product Specification
www.xilinx.com
Send Feedback
22