DS892 Datasheet, PDF (38/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
MMCM Switching Characteristics
Table 36: MMCM Specification
Symbol
Description
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V
Units
-3
-2 -1/-1L -1L
MMCM_F_INMAX
MMCM_F_INMIN
MMCM_F_INJITTER
Maximum input clock frequency
Minimum input clock frequency
Maximum input clock period jitter
Input duty cycle range: 10–49 MHz
1066 933
800
800
MHz
10
10
10
10 MHz
< 20% of clock input period or 1 ns Max
25–75
%
Input duty cycle range: 50–199 MHz
30–70
%
MMCM_F_INDUTY
Input duty cycle range: 200–399 MHz
Input duty cycle range: 400–499 MHz
35–65
%
40–60
%
Input duty cycle range: >500 MHz
45–55
%
MMCM_F_{MIN_PSCLK}
MMCM_F_{MAX_PSCLK}
MMCM_F_VCOMIN
MMCM_F_VCOMAX
MMCM_F_BANDWIDTH
Minimum dynamic phase shift clock frequency
Maximum dynamic phase shift clock frequency
Minimum MMCM VCO frequency
Maximum MMCM VCO frequency
Low MMCM bandwidth at typical⁽¹⁾
High MMCM bandwidth at typical⁽¹⁾
0.01
550
600
1600
1.00
4.00
0.01
500
600
1440
1.00
4.00
0.01
450
600
1200
1.00
4.00
0.01
450
600
1200
1.00
4.00
MHz
MHz
MHz
MHz
MHz
MHz
MMCM_T_{STATPHAOFFSET} Static phase offset of the MMCM outputs⁽²⁾
0.12 0.12 0.12 0.12
ns
MMCM_T_OUTJITTER
MMCM output jitter
Note 3
MMCM_T_OUTDUTY
MMCM output clock duty cycle precision⁽⁴⁾
0.165 0.20 0.20 0.20
ns
MMCM_T_LOCKMAX
MMCM maximum lock time for MMCM_F_PFDMIN
frequencies above 20 MHz
MMCM maximum lock time for MMCM_F_PFDMIN
frequencies from 10 MHz to 20 MHz
100
100
100
100
µs
200
200
200
200
µs
MMCM_F_OUTMAX
MMCM_F_OUTMIN
MMCM_T_EXTFDVAR
MMCM_RST_MINPULSE
MMCM_F_PFDMAX
MMCM maximum output frequency
MMCM minimum output frequency⁽⁴⁾⁽⁵⁾
External clock feedback variation
Minimum reset pulse width
Maximum frequency at the phase frequency
detector
850
725
630
630
MHz
4.69 4.69 4.69 4.69 MHz
< 20% of clock input period or 1 ns Max
5.00 5.00 5.00 5.00
ns
550
500
450
450
MHz
MMCM_F_PFDMIN
Minimum frequency at the phase frequency
detector
10
10
10
10
MHz
MMCM_T_FBDELAY
Maximum delay in the feedback path
5 ns Max or one clock cycle
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter
frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS892 (v1.12) April 1, 2016
Product Specification
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