DS892 Datasheet, PDF (72/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Configuration Switching Characteristics
Table 86: Configuration Switching Characteristics
Symbol
Description
Speed Grades and
V_CCINT Operating Voltages
1.0V
0.95V
0.90V
Units
-3
-2
-1 -1L -1L
Power-up Timing Characteristics
T_PL
T_POR
Program latency
Power-on reset
(40 ms ramp rate time)
Power-on reset with POR override
(2 ms ramp rate time)
7.5
7.5
7.5
7.5
7.5
ms, Max
57
57
57
57
57
ms, Max
0
0
0
0
0
ms, Min
15
15
15
15
15
ms, Max
5
5
5
5
5
ms, Min
T_PROGRAM
Program pulse width
CCLK Output (Master Mode)
250 250 250 250 250
ns, Min
T_ICCK
T_MCCKL(1)
T_MCCKH
Master CCLK output delay from INIT_B
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
SPI x2/x4/x8
BPI x8/x16
150 150 150 150 150
ns, Min
40/60 40/60 40/60 40/60 40/60 %, Min/Max
40/60 40/60 40/60 40/60 40/60 %, Min/Max
150 150 150 150 150 MHz, Max
F_MCCK
Master CCLK frequency
SPI x1 and serial
SLR-based devices
125
125
125
125
125
MHz, Max
SPI x1 and serial
all other devices
150
150
150
150
150
MHz, Max
SelectMAP
125 125 125 125 125 MHz, Max
F_{MCCK_START}
Master CCLK frequency at start of
configuration
3
3
3
3
3
MHz, Typ
F_MCCKTOL
Frequency tolerance, master mode with
respect to nominal CCLK
±35 ±35 ±35 ±35 ±35
%, Max
CCLK Input (Slave Modes)
T_SCCKL
T_SCCKH
Slave CCLK clock minimum Low time
2.5 2.5 2.5 2.5 2.5
ns, Min
Slave CCLK clock minimum High time
2.5 2.5 2.5 2.5 2.5
ns, Min
Serial SLR-based 125 125 125 125 125 MHz, Max
F_SCCK
Slave CCLK frequency
Serial
All other devices
150 150 150 150 150 MHz, Max
SelectMAP
125 125 125 125 125 MHz, Max
DS892 (v1.12) April 1, 2016
Product Specification
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