DS892 Datasheet, PDF (42/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Input Parameter Guidelines
The pin-to-pin numbers in Table 42 through Table 43 are based on the clock root placement in the center
of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 42: Global Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2
-1 -1L -1L
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^(1)(2)(3)
T_{PSMMCMCC_KU025} Global clock input and input
T_{PHMMCMCC_KU025} ^{flip-flop (or latch) with MMCM}
Setup
Hold
XCKU025
N/A
N/A
2.16 2.51
–0.48 –0.48
N/A
N/A
N/A
N/A
ns
ns
T_{PSMMCMCC_KU035}
T_{PHMMCMCC_KU035}
Setup
1.70 1.72 1.74 1.74 2.07 ns
XCKU035
Hold
–0.23 –0.23 –0.23 –0.23 –0.13 ns
T_{PSMMCMCC_KU040}
T_{PHMMCMCC_KU040}
Setup
1.70 1.72 1.74 1.74 2.07 ns
XCKU040
Hold
–0.23 –0.23 –0.23 –0.23 –0.13 ns
T_{PSMMCMCC_KU060}
T_{PHMMCMCC_KU060}
Setup
2.21 2.23 2.51 2.51 2.55 ns
XCKU060
Hold
–0.47 –0.47 –0.47 –0.47 –0.15 ns
T_{PSMMCMCC_KU085}
T_{PHMMCMCC_KU085}
Setup
2.21 2.23 2.51 2.51 2.55 ns
XCKU085
Hold
–0.37 –0.37 –0.37 –0.37 –0.15 ns
T_{PSMMCMCC_KU095}
T_{PHMMCMCC_KU095}
Setup
N/A 2.25 2.55 N/A N/A
ns
XCKU095
Hold
N/A –0.47 –0.47 N/A N/A
ns
T_{PSMMCMCC_KU115}
T_{PHMMCMCC_KU115}
Setup
2.21 2.23 2.51 2.51 2.55 ns
XCKU115
Hold
–0.37 –0.37 –0.37 –0.37 –0.15 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured
relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is
measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS892 (v1.12) April 1, 2016
Product Specification
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