DS892 Datasheet, PDF (52/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 56: GTH Transceiver Receiver Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
J_{T_SJ8.0_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ6.6_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ5.0}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ4.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ4.0L}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.75}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ3.2}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ2.5}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ1.25}
Sinusoidal jitter (CPLL)⁽³⁾
J_{T_SJ500}
Sinusoidal jitter (CPLL)⁽³⁾
SJ Jitter Tolerance with Stressed Eye⁽²⁾
8.0 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
4.0 Gb/s⁽⁴⁾
3.75 Gb/s
3.2 Gb/s⁽⁵⁾
2.5 Gb/s⁽⁶⁾
1.25 Gb/s⁽⁷⁾
500 Mb/s
0.42
0.44
0.44
0.44
0.45
0.44
0.45
0.50
0.50
0.40
J_{T_TJSE3.2}
J_{T_TJSE6.6}
J_{T_SJSE3.2}
J_{T_SJSE6.6}
Total jitter with stressed eye⁽⁸⁾
Sinusoidal jitter with stressed eye⁽⁸⁾
3.2 Gb/s
6.6 Gb/s
3.2 Gb/s
6.6 Gb/s
0.70
0.70
0.10
0.10
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10^–12.
3. The frequency of the injected sinusoidal jitter is 10 MHz.
4. CPLL frequency at 2.0 GHz and RXOUT_DIV = 1
5. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter with RX equalizer enabled. DFE disabled.
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
–
–
–
–
–
–
–
–
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
–
UI
–
UI
–
UI
–
UI
DS892 (v1.12) April 1, 2016
Product Specification
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