DS892 Datasheet, PDF (64/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 73: GTY Transceiver Receiver Switching Characteristics (Cont’d)
Symbol
Description
Condition
Min
J_{T_SJ10.32_CPLL} Sinusoidal jitter (CPLL)⁽³⁾
10.32 Gb/s
–
J_{T_SJ9.8}
Sinusoidal jitter (CPLL)⁽³⁾
9.8 Gb/s
–
J_{T_SJ8.0_QPLL}
Sinusoidal jitter (CPLL)⁽³⁾
8.0 Gb/s
–
J_{T_SJ8.0_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
8.0 Gb/s
–
J_{T_SJ6.6_CPLL}
Sinusoidal jitter (CPLL)⁽³⁾
6.6 Gb/s
–
J_{T_SJ5.0}
Sinusoidal jitter (CPLL)⁽³⁾
5.0 Gb/s
–
J_{T_SJ4.25}
Sinusoidal jitter (CPLL)⁽³⁾
4.25 Gb/s
–
J_{T_SJ4.00L}
Sinusoidal jitter (CPLL)⁽³⁾
4.0 Gb/s
–
J_{T_SJ3.75}
Sinusoidal jitter (CPLL)⁽³⁾
3.75 Gb/s
–
J_{T_SJ3.20}
Sinusoidal jitter (CPLL)⁽³⁾
3.2 Gb/s⁽⁴⁾
–
J_{T_SJ2.5}
Sinusoidal jitter (CPLL)⁽³⁾
2.5 Gb/s⁽⁵⁾
–
J_{T_SJ1.25}
Sinusoidal jitter (CPLL)⁽³⁾
1.25 Gb/s⁽⁶⁾
–
J_{T_SJ500}
Sinusoidal jitter (CPLL)⁽³⁾
500 Mb/s
–
SJ Jitter Tolerance with Stressed Eye⁽²⁾
J_{T_TJSE3.2}
Total jitter with stressed eye⁽⁷⁾
3.2 Gb/s
–
J_{T_TJSE6.6}
6.6 Gb/s
–
J_{T_SJSE3.2}
J_{T_SJSE6.6}
Sinusoidal jitter with stressed eye^{(7) 3.2 Gb/s}
6.6 Gb/s
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10^–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
0.30
0.30
0.44
0.42
0.44
0.44
0.44
0.45
0.45
0.45
0.50
0.50
0.50
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
0.7
UI
0.7
UI
0.7
UI
0.7
UI
DS892 (v1.12) April 1, 2016
Product Specification
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