DS892 Datasheet, PDF (40/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
The pin-to-pin numbers in Table 38 through Table 41 are based on the clock root placement in the center
of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the
Vivado Design Suite timing report for the actual pin-to-pin values.
Table 38: Global Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Symbol
Description
Device
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2
-1 -1L -1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without
MMCM/PLL.
T_ICKOF
Global clock input and output flip-flop without XCKU025 N/A 6.07 7.00 N/A N/A
ns
MMCM/PLL (near clock region)
XCKU035 5.40 6.21 7.05 7.05 7.44 ns
XCKU040 5.40 6.21 7.05 7.05 7.44 ns
XCKU060 5.19 5.99 6.93 6.93 7.19 ns
XCKU085 5.20 6.08 7.08 7.08 7.19 ns
XCKU095 N/A 6.09 7.13 N/A N/A
ns
XCKU115 5.20 6.08 7.08 7.08 7.19 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
Table 39: Global Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Symbol
Description
Device
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2
-1 -1L -1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without
MMCM/PLL.
T_{ICKOF_FAR} Global clock input and output flip-flop without XCKU025 N/A 6.40 7.37 N/A N/A
ns
MMCM/PLL (far clock region)
XCKU035 5.84 6.73 7.64 7.64 8.09 ns
XCKU040 5.84 6.73 7.64 7.64 8.09 ns
XCKU060 5.94 6.84 7.91 7.91 8.22 ns
XCKU085 5.95 6.98 8.12 8.12 8.21 ns
XCKU095 N/A 6.67 7.69 N/A N/A
ns
XCKU115 5.95 6.98 8.12 8.12 8.21 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
DS892 (v1.12) April 1, 2016
Product Specification
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