DS892 Datasheet, PDF (66/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
GTY Transceiver Protocol Jitter Characteristics for the XCKU095
For Table 75 through Table 79, the UltraScale Architecture GTY Transceiver User Guide (UG578) contains
recommended settings for optimal usage of protocol specific characteristics.
Table 75: Gigabit Ethernet Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
Min
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
–
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
0.749
Max
0.24
–
Units
UI
UI
Table 76: XAUI Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
3125
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
Min
–
0.65
Max
0.35
–
Units
UI
UI
Table 77: CEI-6G and CEI-11G Protocol Characteristics (GTY Transceivers)
Description
Line Rate (Mb/s)
Interface
CEI-6G Transmitter Jitter Generation
Total transmitter jitter⁽¹⁾
4976–6375
CEI-6G-SR
CEI-6G-LR
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance⁽¹⁾
4976–6375
CEI-6G-SR
CEI-6G-LR
CEI-11G Transmitter Jitter Generation
Total transmitter jitter⁽²⁾
9950–11100
CEI-11G-SR
CEI-11G-LR/MR
CEI-11G Receiver High Frequency Jitter Tolerance
CEI-11G-SR
Total receiver jitter tolerance⁽²⁾
9950–11100
CEI-11G-MR
CEI-11G-LR
Min
Max Units
–
0.3
UI
–
0.3
UI
0.6
–
UI
0.95
–
UI
–
0.3
UI
–
0.3
UI
0.65
–
UI
0.65
–
UI
0.825
–
UI
Notes:
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference
clock.
DS892 (v1.12) April 1, 2016
Product Specification
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