DS892 Datasheet, PDF (31/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 29 specifies the values of T_{OUTBUF_DELAY_TE_PAD} and T_{INBUF_DELAY_IBUFDIS_O}. T_{OUTBUF_DELAY_TE_PAD} is the
delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e.,
a high impedance state). T_{INBUF_DELAY_IBUFDIS_O} is the IOB delay from IBUFDISABLE to O output. In HP I/O
banks, the internal DCI termination turn-off time is always faster than T_{OUTBUF_DELAY_TE_PAD} when the
DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always
faster than T_{OUTBUF_DELAY_TE_PAD} when the INTERMDISABLE pin is used.
Table 29: IOB 3-state Output Switching Characteristics
Symbol
Description
T_{OUTBUF_DELAY_TE_PAD(1)}
T
T
input to
input to
pad
pad
high-impedance
high-impedance
for
for
HR I/O banks
HP I/O banks
T_{INBUF_DELAY_IBUFDIS_O}
IBUF turn-on time from IBUFDISABLE to O output
for HR I/O banks
IBUF turn-on time from IBUFDISABLE to O output
for HP I/O banks
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2 -1/-1L -1L
1.37 1.52 1.69 1.69
ns
0.62 0.71 0.78 0.78
ns
0.47 0.65 0.68 0.68
ns
1.06 1.21 1.49 1.49
ns
Notes:
1.
The
are
lTa^Org^Ue^Tr^B.^UFU^_s^De^ELt^Ah^Ye^_TV^Ei^_v^Pa^Ad^Dovtaimluiensgarreepaoprtpfliocrabthlee
to single-ended I/O standards. For true differential standards,
most accurate timing values for your configuration.
the
values
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay.
Table 30: Input Delay Measurement Methodology
Description
I/O Standard
Attribute
LVCMOS, 1.2V
LVCMOS12
LVCMOS, LVDCI, HSLVDCI, 1.5V
LVCMOS15,
LVDCI_15,
HSLVDCI_15
LVCMOS, LVDCI, HSLVDCI, 1.8V
LVCMOS18,
LVDCI_18,
HSLVDCI_18
LVCMOS, 2.5V
LVCMOS25
LVCMOS, 3.3V
LVCMOS33
LVTTL, 3.3V
LVTTL
HSTL (high-speed transceiver logic),
Class I, 1.2V
HSTL_I_12
HSTL, Class I and II, 1.5V
HSTL_I, HSTL_II
HSTL, Class I and II, 1.8V
HSTL_I_18,
HSTL_II_18
HSUL (high-speed unterminated logic), 1.2V HSUL_12
SSTL (stub series terminated logic), 1.2V
SSTL12
V_L(1)(2)
0.1
0.1
V_H(1)(2)
1.1
(1^V)M(4E)A(S6) (1^V)(R3E)F(5)
0.6
–
1.4
0.75
–
0.1
1.7
0.9
0.1
2.4
0.1
3.2
0.1
3.2
V_REF – 0.5 V_REF + 0.5
V_REF – 0.65 V_REF + 0.65
V_REF – 0.8 V_REF + 0.8
V_REF – 0.5
V_REF – 0.5
V_REF + 0.5
V_REF + 0.5
1.25
1.65
1.65
V_REF
V_REF
V_REF
V_REF
V_REF
–
–
–
–
0.60
0.75
0.90
0.60
0.60
DS892 (v1.12) April 1, 2016
Product Specification
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