DS892 Datasheet, PDF (41/79 Pages) Xilinx, Inc – DC and AC Switching Characteristics

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics
Table 40: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2
-1 -1L -1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
T_ICKOFMMCMCC Global clock input and output flip-flop with XCKU025 N/A 1.80 1.88 N/A N/A
ns
MMCM
XCKU035 2.13 2.45 2.78 2.78 3.72 ns
XCKU040 2.13 2.45 2.78 2.78 3.72 ns
XCKU060 1.58 1.92 2.05 2.05 2.41 ns
XCKU085 1.58 1.95 2.12 2.12 2.41 ns
XCKU095 N/A 1.59 1.85 N/A N/A
ns
XCKU115 1.58 1.95 2.12 2.12 2.41 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. MMCM output jitter is already included in the timing calculation.
Table 41: Global Clock Input to Output Delay With PLL
Symbol
Description
Device
Speed Grade and V_CCINT
Operating Voltages
1.0V
0.95V
0.90V ^Units
-3
-2
-1 -1L -1L
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
T_{ICKOF_PLL_CC} Global clock input and output flip-flop with XCKU025 N/A 5.39 6.11 N/A N/A
ns
PLL
XCKU035 4.25 4.46 5.08 5.08 5.46 ns
XCKU040 4.25 4.46 5.08 5.08 5.46 ns
XCKU060 5.13 5.83 6.66 6.66 6.95 ns
XCKU085 5.14 5.96 6.85 6.85 6.96 ns
XCKU095 N/A 5.70 6.49 N/A N/A
ns
XCKU115 5.14 5.96 6.85 6.85 6.96 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. PLL output jitter is already included in the timing calculation.
DS892 (v1.12) April 1, 2016
Product Specification
www.xilinx.com
Send Feedback
41