XQ5VLX30T Datasheet, PDF (72/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5Q FPGA source-
synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
Symbol
T_{DCD_CLK}
T_CKSKEW
Description
Global Clock Tree Duty Cycle Distortion⁽¹⁾
Global Clock Tree Skew⁽²⁾
Device
All
XQ5VLX30T
XQ5VLX85
Speed Grade
-2I
-1I
-1M
0.12
0.12
0.12
0.22
0.22
N/A
0.43
0.45
N/A
Units
ns
ns
ns
XQ5VLX110
0.50
0.51
N/A
ns
XQ5VLX110T
0.50
0.51
N/A
ns
XQ5VLX155T
0.85
0.88
N/A
ns
XQ5VLX220T
1.07
1.10
N/A
ns
XQ5VLX330T
N/A
1.29
N/A
ns
XQ5VSX50T
0.44
0.45
N/A
ns
XQ5VSX95T
0.72
0.74
N/A
ns
XQ5VSX240T
N/A
1.36
N/A
ns
XQ5VFX70T
0.42
0.43
0.43
ns
XQ5VFX100T
0.84
0.86
0.86
ns
XQ5VFX130T
0.84
0.86
N/A
ns
XQ5VFX200T
N/A
1.29
N/A
ns
T_{DCD_BUFIO}
T_BUFIOSKEW
T_{DCD_BUFR}
I/O clock tree duty cycle distortion
All
I/O clock tree skew across one clock region
All
Regional clock tree duty cycle distortion
All
0.10
0.10
0.10
ns
0.07
0.08
0.08
ns
0.25
0.25
0.25
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T_CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
72