XQ5VLX30T Datasheet, PDF (61/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL
in System-Synchronous Mode
T_ICKOFPLL
Global Clock and OUTFF with PLL
XQ5VLX30T
XQ5VLX85
2.30
2.70
N/A
2.49
2.88
N/A
XQ5VLX110
2.53
2.92
N/A
XQ5VLX110T
2.53
2.92
N/A
XQ5VLX155T
2.60
3.01
N/A
XQ5VLX220T
2.74
3.12
N/A
XQ5VLX330T
N/A
3.27
N/A
XQ5VSX50T
2.36
2.76
N/A
XQ5VSX95T
2.29
2.69
N/A
XQ5VSX240T
N/A
3.34
N/A
XQ5VFX70T
2.71
3.10
3.10
XQ5VFX100T
2.70
3.10
3.10
XQ5VFX130T
2.75
3.17
N/A
XQ5VFX200T
N/A
3.35
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
61