XQ5VLX30T Datasheet, PDF (27/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 52: Register-to-Register Performance (Cont’d)
Description
Distributed RAM
Single-Port 16 x 8
Single-Port 32 x 8
Single-Port 64 x 8
Dual-Port 16 x 8
Shift Register Chain
16-bit
32-bit
64-bit
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
DSP48E Dual 24-bit Adder/Subtracter
DSP48E 48-bit Adder/Subtracter
DSP48E 48-bit Counter
DSP48E 48-bit Comparator
DSP48E 25 x 18 bit Pipelined Multiplier
DSP48E Direct 4-tap FIR Filter Pipelined
DSP48E Systolic n-tap FIR Filter Pipelined
Notes:
1. Device used is the XQ5VLX50T- FF1136.
Register-to-Register
(with I/O Delays)
Speed Grade
-2I
-1I
-1M
500
450
450
500
450
450
500
450
450
500
450
450
500
450
450
500
438
438
500
450
450
500
450
450
500
450
450
500
450
450
500
450
450
500
450
450
458
397
397
500
450
450
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 53: Interface Performances
Description
Networking Applications
SFI-4.1 (SDR LVDS Interface)⁽¹⁾
SPI-4.2 (DDR LVDS Interface)⁽²⁾
Memory Interfaces
DDR⁽³⁾
DDR2⁽⁴⁾
QDR II SRAM⁽⁵⁾
RLDRAM II⁽⁶⁾
-2I
710 MHz
1.25 Gb/s
200 MHz
300 MHz
300 MHz
300 MHz
Speed Grade
-1I
645 MHz
1.0 Gb/s
200 MHz
267 MHz
250 MHz
250 MHz
-1M
645 MHz
1.0 Gb/s
200 MHz
267 MHz
250 MHz
250 MHz
Notes:
1. Performance defined using design implementation described in application note XAPP856, SFI-4.1 16-Channel SDR Interface with
Bus Alignment.
2. Performance defined using design implementation described in application note XAPP860, 16-Channel, DDR LVDS Interface with
Real-time Window Monitoring.
3. Performance defined using design implementation described in application note XAPP851, DDR SDRAM Controller.
4. Performance defined using design implementation described in application note XAPP858, High-Performance DDR2 SDRAM
Interface Data Capture.
5. Performance defined using design implementation described in application note XAPP853, QDRII SRAM Interface.
6. Performance defined using design implementation described in application note XAPP852, Synthesizable RLDRAM II Controller.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
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