XQ5VLX30T Datasheet, PDF (49/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Devices
T_{BCCCK_CE}/T_{BCCKC_CE(1)}
T_{BCCCK_S}/T_{BCCKC_S(1)}
T_{BCCKO_O(2)}
Maximum Frequency
F_MAX
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from
I0/I1 to O
All
All
LX30T, LX85, LX110, LX110T,
SX50T, FX70T, FX100T, and
FX130T
LX155T
LX220T, LX330T, SX95T,
SX240T, and FX200T
Global clock tree (BUFG)
LX30T, LX85, LX110, LX110T,
SX50T, and FX70T(I)
LX155T, FX70T(M), and
FX100T
FX130T
LX220T, LX330T, SX95T,
SX240T, and FX200T
Speed Grade
-2I
-1I
-1M
0.27
0.31
0.31
0.00
0.00
0.00
0.27
0.31
0.31
0.00
0.00
0.00
0.22
0.25
0.25
0.14
0.30
N/A
0.22
0.25
N/A
667
600
N/A
600
550
550
500
450
N/A
500
450
N/A
Units
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
2. T_{BGCKO_O} (BUFG delay from I0 to O) values are the same as T_{BCCKO_O} values.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
T_{BUFIOCKO_O}
Maximum Frequency
F_MAX
Clock to out delay from I to O
I/O clock tree (BUFIO)
Speed Grade
-2I
-1I
-1M
1.16
1.29
1.29
Units
ns
710
644
644
MHz
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
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