XQ5VLX30T Datasheet, PDF (62/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 88: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL
in Source-Synchronous Mode
T_{ICKOFPLL_0}
Global Clock and OUTFF with PLL
XQ5VLX30T
XQ5VLX85
4.32
4.82
N/A
4.40
4.88
N/A
XQ5VLX110
4.44
4.92
N/A
XQ5VLX110T
4.44
4.92
N/A
XQ5VLX155T
4.66
5.16
N/A
XQ5VLX220T
4.85
5.29
N/A
XQ5VLX330T
N/A
5.44
N/A
XQ5VSX50T
4.54
5.02
N/A
XQ5VSX95T
4.68
5.14
N/A
XQ5VSX240T
N/A
5.51
N/A
XQ5VFX70T
4.54
5.02
5.02
XQ5VFX100T
4.70
5.19
5.19
XQ5VFX130T
4.86
5.40
N/A
XQ5VFX200T
N/A
5.55
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
62