XQ5VLX30T Datasheet, PDF (33/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 56: IOB Switching Characteristics (Cont’d)
I/O Standard
T_IOPI
Speed Grade
-2(I)
-1(I) -1(M)
HSTL_I_12
0.85 1.00 1.08
HSTL_I_DCI
0.85 1.00 1.07
HSTL_II_DCI
0.85 1.00 1.05
HSTL_II_T_DCI
0.85 1.00 1.05
HSTL_III_DCI
0.85 1.00 1.40
HSTL_IV_DCI
0.85 1.00 1.40
HSTL_I_DCI_18
0.85 1.00 1.26
HSTL_II_DCI_18
0.85 1.00 1.13
HSTL_II _T_DCI_18
0.85 1.00 1.13
HSTL_III_DCI_18
0.85 1.00 1.45
HSTL_IV_DCI_18
0.85 1.00 1.45
DIFF_HSTL_I_18
0.90 1.06 1.10
DIFF_HSTL_I_DCI_18
0.90 1.06 1.10
DIFF_HSTL_I
0.90 1.06 1.10
DIFF_HSTL_I_DCI
0.90 1.06 1.10
DIFF_HSTL_II_18
0.90 1.06 1.10
DIFF_HSTL_II_DCI_18
0.90 1.06 1.10
DIFF_HSTL_II
0.90 1.06 1.10
DIFF_HSTL_II_DCI
0.90 1.06 1.10
SSTL2_I_DCI
0.85 1.00 1.11
SSTL2_II_DCI
0.85 1.00 1.11
SSTL2_II_T_DCI
0.85 1.00 1.11
SSTL18_I
0.85 1.00 1.08
SSTL18_II
0.85 1.00 1.08
SSTL18_I_DCI
0.85 1.00 1.08
SSTL18_II_DCI
0.85 1.00 1.08
SSTL18_II_T_DCI
0.85 1.00 1.08
DIFF_SSTL2_I
0.90 1.06 1.11
DIFF_SSTL2_I_DCI
0.90 1.06 1.11
DIFF_SSTL18_I
0.90 1.06 1.10
DIFF_SSTL18_I_DCI
0.90 1.06 1.10
DIFF_SSTL2_II
0.90 1.06 1.11
DIFF_SSTL2_II_DCI
0.90 1.06 1.11
DIFF_SSTL18_II
0.90 1.06 1.10
DIFF_SSTL18_II_DCI
0.90 1.06 1.10
T_IOOP
Speed Grade
-2(I) -1(I) -1(M)
1.61 1.85 1.98
1.56 1.77 1.98
1.48 1.69 1.86
1.56 1.77 1.98
1.72 1.95 2.27
1.46 1.64 1.84
1.50 1.70 1.95
1.43 1.64 1.77
1.50 1.70 1.95
1.69 1.91 2.16
1.44 1.62 1.84
1.55 1.77 1.91
1.50 1.70 1.91
1.57 1.79 1.91
1.56 1.77 1.95
1.51 1.72 1.91
1.43 1.64 1.91
1.53 1.74 1.91
1.48 1.69 1.91
1.56 1.78 3.30
1.48 1.70 1.97
1.56 1.78 3.30
1.61 1.84 1.94
1.53 1.75 1.81
1.53 1.74 1.97
1.44 1.64 1.86
1.53 1.74 1.97
1.64 1.87 1.97
1.56 1.78 1.94
1.61 1.84 1.94
1.53 1.74 1.94
1.55 1.76 1.91
1.48 1.70 1.90
1.53 1.75 1.91
1.44 1.64 1.91
T_IOTP
Speed Grade
-2(I) -1(I) -1(M)
1.61 1.85 1.98
1.56 1.77 1.98
1.48 1.69 1.86
1.56 1.77 1.98
1.72 1.95 2.27
1.46 1.64 1.84
1.50 1.70 1.95
1.43 1.64 1.77
1.50 1.70 1.95
1.69 1.91 2.16
1.44 1.62 1.84
1.55 1.77 1.91
1.50 1.70 1.91
1.57 1.79 1.91
1.56 1.77 1.95
1.51 1.72 1.91
1.43 1.64 1.91
1.53 1.74 1.91
1.48 1.69 1.91
1.56 1.78 3.30
1.48 1.70 1.97
1.56 1.78 3.30
1.61 1.84 1.94
1.53 1.75 1.81
1.53 1.74 1.97
1.44 1.64 1.86
1.53 1.74 1.97
1.64 1.87 1.97
1.56 1.78 1.94
1.61 1.84 1.94
1.53 1.74 1.94
1.55 1.76 1.91
1.48 1.70 1.90
1.53 1.75 1.91
1.44 1.64 1.91
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. M-temperature IOB delays are slightly larger than timing analyzer/speeds specification values. Correct values are listed in this table. It is
necessary to allow for this difference in the design.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
33