XQ5VLX30T Datasheet, PDF (20/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 6
+V
P
N
0
X-Ref Target - Figure 7
+V
Figure 6: Single-Ended Output Voltage Swing
V_SEOUT
ds714_06_012109
0
DV_PPOUT
DV_PPIN
–V
P–N
Figure 7: Peak-to-Peak Differential Output Voltage
ds714_07_012109
Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTX
Transceiver User Guide for further details.
Table 41: GTX_DUAL Tile Clock DC Input Level Specification⁽¹⁾
Symbol
DC Parameter
Conditions
V_IDIFF
V_ISE
R_IN
C_EXT
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
Notes:
1. V_MIN = 0V and V_MAX = 1200 mV
Min Typ
210 800
105 400
90
105
100
Max
2000
750
130
Units
mV
mV
Ω
nF
X-Ref Target - Figure 8
+V
P
N
0
X-Ref Target - Figure 9
+V
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
P–N
V_ISE
ds714_08_012109
0
V_IDIFF
–V
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
DS714 (v2.1) July 23, 2010
Product Specification
www.xilinx.com
ds714_09_012109
20