XQ5VLX30T Datasheet, PDF (41/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 65: CLB Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-2I
-1I
-1M
Units
T_BXD
T_CXB
T_CXD
T_DXD
T_OPCYA
T_OPCYB
T_OPCYC
T_OPCYD
T_AXCY
T_BXCY
T_CXCY
T_DXCY
T_BYP
T_CINA
T_CINB
T_CINC
T_CIND
Sequential Delays
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
0.51
0.59
0.59
ns, Max
0.36
0.42
0.42
ns, Max
0.42
0.49
0.49
ns, Max
0.42
0.49
0.49
ns, Max
0.50
0.59
0.59
ns, Max
0.44
0.51
0.51
ns, Max
0.37
0.43
0.43
ns, Max
0.34
0.40
0.40
ns, Max
0.42
0.50
0.50
ns, Max
0.30
0.37
0.37
ns, Max
0.22
0.26
0.26
ns, Max
0.22
0.26
0.26
ns, Max
0.10
0.11
0.11
ns, Max
0.27
0.31
0.31
ns, Max
0.30
0.35
0.35
ns, Max
0.32
0.36
0.36
ns, Max
0.35
0.41
0.41
ns, Max
T_CKO
Clock to AQ – DQ outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
0.40
0.47
0.47
ns, Max
T_DICK/T_CKDI
AX – DX input to CLK on A – D Flip Flops
0.41
0.49
0.49
ns, Min
0.21
0.24
0.31
T_RCK
T_CECK/T_CKCE
DX input to CLK when used as REV
CE input to CLK on A – D Flip Flops
0.42
0.20
–0.04
0.51
0.23
–0.04
0.51
0.23
–0.03
ns, Min
ns, Min
T_SRCK/T_CKSR
SR input to CLK on A – D Flip Flops
0.49
–0.19
0.59
–0.19
0.59
–0.19
ns, Min
T_CINCK/T_CKCIN
CIN input to CLK on A – D Flip Flops
0.16
0.18
0.18
ns, Min
0.16
0.19
0.26
Set/Reset
T_SRMIN
T_RQ
T_CEO
F_TOG
SR input minimum pulse width
Delay from SR or REV input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
0.90
0.86
0.52
1265
0.90
1.03
0.63
1098
0.90
1.03
0.63
1098
ns, Min
ns, Max
ns, Max
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0”
is listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
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