XQ5VLX30T Datasheet, PDF (58/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 84. Values are expressed in nanoseconds unless otherwise noted.
Table 84: Global Clock Input to Output Delay Without DCM or PLL
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
T_ICKOF
Global Clock and OUTFF without DCM or PLL
XQ5VLX30T
XQ5VLX85
6.04
6.73
N/A
6.28
6.99
N/A
XQ5VLX110
6.35
7.06
N/A
XQ5VLX110T
6.35
7.06
N/A
XQ5VLX155T
6.68
7.52
N/A
XQ5VLX220T
6.99
7.71
N/A
XQ5VLX330T
N/A
7.91
N/A
XQ5VSX50T
6.27
6.97
N/A
XQ5VSX95T
6.59
7.30
N/A
XQ5VSX240T
N/A
7.98
N/A
XQ5VFX70T
6.33
7.04
7.04
XQ5VFX100T
6.73
7.44
7.44
XQ5VFX130T
6.80
7.52
N/A
XQ5VFX200T
N/A
7.91
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
58