XQ5VLX30T Datasheet, PDF (59/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in System-Synchronous Mode
T_ICKOFDCM
Global Clock and OUTFF with DCM
XQ5VLX30T
XQ5VLX85
2.56
2.93
N/A
2.63
3.00
N/A
XQ5VLX110
2.69
3.06
N/A
XQ5VLX110T
2.69
3.06
N/A
XQ5VLX155T
2.74
3.10
N/A
XQ5VLX220T
2.83
3.18
N/A
XQ5VLX330T
N/A
3.37
N/A
XQ5VSX50T
2.69
3.05
N/A
XQ5VSX95T
2.64
3.00
N/A
XQ5VSX240T
N/A
3.36
N/A
XQ5VFX70T
2.74
3.12
3.12
XQ5VFX100T
2.59
3.00
3.00
XQ5VFX130T
2.67
3.07
N/A
XQ5VFX200T
N/A
3.27
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
59