XQ5VLX30T Datasheet, PDF (50/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 73: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
Devices
LX30T, LX85, LX110, LX110T, SX50T,
FX100T, and FX130T
T_{BRCKO_O}
Clock to out delay from I to O
FX70T
LX155T
LX220T, LX330T, SX95T, SX240T, and
FX200T
T_{BRCKO_O_BYP}
Clock to out delay from I to O with
Divide Bypass attribute set
LX30T, LX85, LX110, LX110T, SX50T,
FX70T, FX100T, and FX130T
LX155T
LX220T, LX330T, SX95T, SX240T, and
FX200T
T_{BRDO_CLRO} Propagation delay from CLR to O All
Maximum Frequency
F_MAX
Regional clock tree (BUFR)
All
Speed Grade
-2I
-1I
-1M
0.59 0.67 0.67
Units
ns
0.74 0.83 0.83 ns
0.80
0.90
N/A
ns
0.59 0.67
N/A
ns
0.24 0.26 0.26 ns
0.26
0.30
N/A
ns
0.24 0.26
N/A
ns
0.70 0.82 0.82 ns
250
250
250 MHz
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
50