XQ5VLX30T Datasheet, PDF (43/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Symbol
Description
Block RAM and FIFO Clock to Out Delays
T_{RCKO_DO} and T_{RCKO_DOR(1)}
Clock CLK to DOUT output (without output register)^{(2, 3)}
Clock CLK to DOUT output (with output register)^{(4, 5)}
Clock CLK to DOUT output with ECC (without output
register)^{(2, 3)}
Clock CLK to DOUT output with ECC (with output
register)^{(4, 5)}
Clock CLK to DOUT output with Cascade (without output
register)⁽²⁾
T_{RCKO_FLAGS}
T_{RCKO_POINTERS}
T_{RCKO_ECCR}
T_{RCKO_ECC}
Clock CLK to DOUT output with Cascade (with output
register)⁽⁴⁾
Clock CLK to FIFO flags outputs⁽⁶⁾
Clock CLK to FIFO pointer outputs⁽⁷⁾
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
Setup and Hold Times Before/After Clock CLK
T_{RCCK_ADDR}/T_{RCKC_ADDR}
ADDR inputs⁽⁸⁾
T_{RDCK_DI}/T_{RCKD_DI}
DIN inputs⁽⁹⁾
T_{RDCK_DI_ECC}/T_{RCKD_DI_ECC}
DIN inputs with ECC in standard mode⁽⁹⁾
DIN inputs with ECC encode only⁽⁹⁾
T_{RCCK_EN}/T_{RCKC_EN}
T_{RCCK_REGCE}/T_{RCKC_REGCE}
T_{RCCK_SSR}/T_{RCKC_SSR}
T_{RCCK_WE}/T_{RCKC_WE}
T_{RCCK_WREN}/T_{RCKC_WREN}
Reset Delays
T_{RCO_FLAGS}
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
WREN/RDEN FIFO inputs⁽¹⁰⁾
Reset RST to FIFO Flags/Pointers⁽¹¹⁾
Speed Grade
-2I
-1I
-1M
Units
1.92 2.19 2.19 ns, Max
0.69 0.82 0.82 ns, Max
3.03 3.61 3.61 ns, Max
0.77 0.93 0.93 ns, Max
2.44 2.94 2.94 ns, Max
1.07 1.30 1.30 ns, Max
0.87 1.02 1.02 ns, Max
1.26 1.48 1.48 ns, Max
0.77 0.93 0.93 ns, Max
2.85 3.41 3.41 ns, Max
1.47 1.74 1.74 ns, Max
0.89 1.05 1.05 ns, Max
0.40 0.48 0.48 ns, Min
0.32 0.36 0.36
0.30 0.35 0.35 ns, Min
0.28 0.29 0.29
0.37 0.42 0.42 ns, Min
0.33 0.36 0.47
0.72 0.77 0.77 ns, Min
0.33 0.36 0.47
0.36 0.42 0.42 ns, Min
0.15 0.15 0.15
0.16 0.18 0.18 ns, Min
0.24 0.27 0.27
0.21 0.26 0.26 ns, Min
0.25 0.28 0.28
0.51 0.63 0.63 ns, Min
0.17 0.18 0.18
0.41 0.48 0.48 ns, Min
0.34 0.40 0.40
1.26 1.48 1.48 ns, Max
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
43