XQ5VLX30T Datasheet, PDF (30/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 56 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T_IOPI is described as the delay from IOB pad through the
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T_IOOP is described as the delay from the O pin to the IOB
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
T_IOTP is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 57, page 34 summarizes the value of T_IOTPHZ.
T_IOTPHZ is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
Table 56: IOB Switching Characteristics
I/O Standard
T_IOPI
Speed Grade
-2(I)
-1(I) -1(M)
LVDS_25
0.90 1.06 1.11
LVDSEXT_25
1.16 1.30 1.36
HT_25
0.90 1.06 1.11
BLVDS_25
0.90 1.06 1.12
RSDS_25 (point to point)
0.90 1.06 1.11
ULVDS_25
0.90 1.06 1.11
PCI33_3
0.70 0.82 1.05
PCI66_3
0.70 0.82 1.05
PCI-X
0.70 0.82 1.05
GTL
0.85 1.00 1.11
GTLP
0.85 1.00 1.05
HSTL_I
0.85 1.00 1.07
HSTL_II
0.85 1.00 1.05
HSTL_III
0.85 1.00 1.40
HSTL_IV
0.85 1.00 1.40
HSTL_I _18
0.85 1.00 1.26
HSTL_II _18
0.85 1.00 1.13
HSTL_III _18
0.85 1.00 1.45
HSTL_IV_18
0.85 1.00 1.45
SSTL2_I
0.85 1.00 1.11
SSTL2_II
0.85 1.00 1.11
LVTTL, Slow, 2 mA
0.70 0.82 1.02
LVTTL, Slow, 4 mA
0.70 0.82 1.02
LVTTL, Slow, 6 mA
0.70 0.82 1.02
LVTTL, Slow, 8 mA
0.70 0.82 1.02
LVTTL, Slow, 12 mA
0.70 0.82 1.02
LVTTL, Slow, 16 mA
0.70 0.82 1.02
LVTTL, Slow, 24 mA
0.70 0.82 1.02
T_IOOP
Speed Grade
-2(I) -1(I) -1(M)
1.29 1.44 1.79
1.34 1.49 1.82
1.26 1.40 1.79
1.38 1.58 1.91
1.29 1.44 1.79
1.27 1.41 1.79
2.06 2.38 2.41
2.06 2.38 2.41
1.56 1.80 2.03
1.63 1.86 2.10
1.68 1.93 2.14
1.57 1.79 1.96
1.53 1.74 1.84
1.60 1.85 2.03
1.60 1.83 2.07
1.55 1.77 1.91
1.51 1.72 1.79
1.61 1.85 1.98
1.57 1.81 1.92
1.64 1.78 1.94
1.55 1.76 1.83
4.47 5.01 6.05
3.09 3.41 4.13
2.91 3.29 3.91
2.30 2.61 2.91
2.15 2.46 2.56
2.04 2.34 2.47
2.07 2.38 2.48
T_IOTP
Speed Grade
-2(I) -1(I) -1(M)
1.29 1.44 1.79
1.34 1.49 1.82
1.26 1.40 1.79
1.38 1.58 1.91
1.29 1.44 1.79
1.27 1.41 1.79
2.06 2.38 2.41
2.06 2.38 2.41
1.56 1.80 2.03
1.63 1.86 2.10
1.68 1.93 2.14
1.57 1.79 1.96
1.53 1.74 1.84
1.60 1.85 2.03
1.60 1.83 2.07
1.55 1.77 1.91
1.51 1.72 1.79
1.61 1.85 1.98
1.57 1.81 1.92
1.64 1.78 1.94
1.55 1.76 1.83
4.47 5.01 6.05
3.09 3.41 4.13
2.91 3.29 3.91
2.30 2.61 2.91
2.15 2.46 2.56
2.04 2.34 2.47
2.07 2.38 2.48
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
30