XQ5VLX30T Datasheet, PDF (25/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min Typ
AV_DD = 2.5V ± 2%, V_REFP = 2.5V, V_REFN = 0V, ADCCLK = 5.2 MHz, T_A = T_MIN to T_MAX, Typical values at T_A=+25°C
DC Accuracy: All external input channels such as V_P/V_N and V_AUXP[15:0]/V_AUXN[15:0], Unipolar Mode,
and Common Mode = 0V
Resolution
10
Integral Nonlinearity
INL
Differential Nonlinearity
Unipolar Offset Error⁽¹⁾
Bipolar Offset Error⁽¹⁾
Gain Error⁽¹⁾
Bipolar Gain Error⁽¹⁾
DNL
Total Unadjusted Error
(Uncalibrated)
Total Unadjusted Error
(Calibrated)
Calibrated Gain Temperature
Coefficient
DC Common-Mode Reject
Conversion Rate⁽²⁾
TUE
TUE
CMRR_DC
No missing codes (T_MIN to T_MAX)
Guaranteed Monotonic
Uncalibrated
Uncalibrated measured in bipolar mode
Uncalibrated, T_j = –40°C to 100°C
Uncalibrated, T_j = –55°C to 125°C
Uncalibrated measured in bipolar mode,
T_j = –40°C to 100°C
Uncalibrated measured in bipolar mode,
T_j = –55°C to 125°C
Deviation from ideal transfer function.
V_REFP – V_REFN = 2.5V
Deviation from ideal transfer function.
V_REFP – V_REFN = 2.5V
Variation of FS code with temperature
V_N = V_CM = 0.5V ± 0.5V,
V_P – V_N = 100mV
±2
±2
±0.2
±0.2
±0.2
±0.2
±10
±1
±0.01
70
Conversion Time - Continuous t_CONV
Number of CLK cycles
26
Conversion Time - Event
t_CONV
Number of CLK cycles
T/H Acquisition Time
t_ACQ
Number of CLK cycles
4
DRP Clock Frequency
DCLK
DRP clock frequency
8
ADC Clock Frequency
CLK Duty cycle
Analog Inputs⁽³⁾
ADCCLK
Derived from DCLK, T_j = –40°C to 100°C
1
Derived from DCLK, T_j = –55°C to 125°C
2.5
40
Dedicated Analog Inputs
Input Voltage Range
V_P - V_N
Unipolar Operation
Differential Inputs
Unipolar Common Mode Range (FS input)
0
–0.25
0
Differential Common Mode Range (FS input)
+0.3
Bandwidth
20
Auxiliary Analog Inputs
Input Voltage Range
V_AUXP[0] /V_AUXN[0] to V_AUXP[15]
/V_AUXN[15]
Unipolar Operation
Differential Operation
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
0
–0.25
0
+0.3
Bandwidth
10
Input Leakage Current
A/D not converting, ADCCLK stopped
±1.0
Input Capacitance
10
On-chip Supply Monitor Error
V_CCINT and V_CCAUX with calibration enabled
Max Units
±2
±0.9
Bits
LSBs
LSBs
±30
±30
±2.0
±2.5
±2.0
LSBs
LSBs
%
%
%
±2.5
%
LSBs
±2 LSBs
LSB/°
C
dB
32
21
250 MHz
5.2 MHz
5.2 MHz
60
%
1
+0.25
+0.5
+0.7
1
+0.25
+0.5
+0.7
±1.0
V
MHz
Volts
kHz
µA
pF
%
Reading
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
25