XQ5VLX30T Datasheet, PDF (54/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode⁽⁵⁾
Symbol
Description
Speed Grade
-2I
-1I
-1M
Units
Outputs Clocks (Low Frequency Mode)
F_1XMRMIN
F_1XMRMAX
F_2XMRMIN
F_2XMRMAX
F_DLLMRMIN
F_DLLMRMAX
F_FXMRMIN
F_FXMRMAX
Input Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
19.00
32.00
38.00
64.00
1.19
21.34
19.00
40.00
19.00
32.00
38.00
64.00
1.19
21.34
19.00
40.00
19.00
32.00
38.00
64.00
1.19
21.34
19.00
40.00
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
F_{CLKINDLLMRMIN}
F_{CLKINDLLMRMAX}
F_CLKINFXMRMIN
F_CLKINFXMRMAX
F_PSCLKMRMIN
F_PSCLKMRMAX
CLKIN (using DLL outputs)^{(1, 3, 4)}
CLKIN (using DFS outputs only)^{(2, 3, 4)}
PSCLK
19.00
32.00
1.00
40.00
1.00
270.00
19.00
32.00
1.00
40.00
1.00
240.00
19.00
32.00
1.00
40.00
1.00
240.00
MHz
MHz
MHz
MHz
KHz
MHz
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
5. Maximum range is not available outside of I-temperature conditions.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
54