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XQ5VLX30T Datasheet, PDF (36/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 59: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
RREF
( Ω)
HSTL, Class IV
HSTL_IV
25
HSTL, Class I, 1.8V
HSTL_I_18
50
HSTL, Class II, 1.8V
HSTL_II_18
25
HSTL, Class III, 1.8V
HSTL_III_18
50
HSTL, Class IV, 1.8V
HSTL_IV_18
25
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
50
SSTL, Class II, 1.8V
SSTL18_II
25
SSTL, Class I, 2.5V
SSTL2_I
50
SSTL, Class II, 2.5V
SSTL2_II
25
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
100
LVDSEXT (LVDS Extended Mode), 2.5V
LVDS_25
100
BLVDS (Bus LVDS), 2.5V
BLVDS_25
100
LDT (HyperTransport), 2.5V
LDT_25
100
LVPECL (Low-Voltage Positive Emitter-Coupled Logic), LVPECL_25
100
2.5V
LVDCI/HSLVDCI
LVDCI_33, HSLVDCI_33
1M
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
1M
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
1M
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
1M
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
50
HSTL, Class III & IV, with DCI
HSTL_III_DCI, HSTL_IV_DCI
50
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18 50
HSTL, Class III & IV, 1.8V, with DCI
HSTL_III_DCI_18,
50
HSTL_IV_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
50
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
50
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
50
GTL Plus with DCI
GTLP_DCI
50
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
4. The value given is the differential input voltage.
CREF(1)
( pF )
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VMEAS
(V)
0.9
VREF
VREF
1.1
1.1
VREF
VREF
VREF
VREF
0(4)
0(4)
0(4)
0(4)
0(4)
1.65
1.25
0.9
0.75
VREF
0.9
VREF
1.1
VREF
VREF
0.8
1.0
VREF
(V)
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.25
1.25
1.2
1.2
0
0.6
0
0
0
0
0
0.75
1.5
0.9
1.8
0.9
1.25
1.2
1.5
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
36
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