XQ5VLX30T Datasheet, PDF (26/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 51: Analog-to-Digital Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min Typ Max Units
On-chip Temperature Monitor
Error
External Reference Inputs⁽⁴⁾
–40°C to +125°C with calibration enabled
±4
°C
Positive Reference Input Voltage V_REFP
Range
Measured Relative to V_REFN
2.45 2.5 2.55 Volts
Negative Reference Input
Voltage Range
Input current
Power Requirements
V_REFN
I_REF
Measured Relative to AGND
ADCCLK = 5.2 MHz
–50
0
100 mV
100
µA
Analog Power Supply
Analog Supply Current
AV_DD
AI_DD
Measured Relative to AV_SS
ADCCLK = 5.2 MHz
2.45 2.5 2.55
V
5
13
mA
Notes:
1. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See Virtex-5 FPGA System Monitor
User Guide.
2. See “System Monitor Timing” in Virtex-5 FPGA System Monitor User Guide.
3. See “Analog Inputs” in Virtex-5 FPGA System Monitor User Guide for a detailed description.
4. Any variation in the reference voltage from the nominal V_REFP = 2.5V and V_REFN = 0V will result is a deviation from the ideal transfer function.
This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric
type applications allowing the supply voltage and reference to vary by ±2% is permitted.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-5Q
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics. Table 52 shows internal (register-to-register) performance.
Table 52: Register-to-Register Performance
Description
Basic Functions
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
9 x 9 Logic Multiplier with 4 pipestages
9 x 9 Logic Multiplier with 5 pipestages
16-bit Adder
32-bit Adder
64-bit Adder
Register to LUT to Register
16-bit Counter
32-bit Counter
64-bit Counter
Memory
Cascaded block RAM (64K)
Block RAM Pipelined
Single-Port 512 x 36 bits
Single-Port 4096 x 4 bits
Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits
Register-to-Register
(with I/O Delays)
Speed Grade
-2I
-1I
-1M
500
450
450
500
450
450
467
407
407
438
428
428
500
428
428
500
450
450
500
447
447
377
323
323
500
450
450
500
450
450
500
450
450
381
333
333
450
400
400
500
450
450
500
450
450
500
450
450
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
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