XQ5VLX30T Datasheet, PDF (71/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 97: Global Clock Setup and Hold with DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾ Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics.
T_{PSDCMPLL_0}/
T_{PHDCMPLL_0}
No Delay Global Clock and IFF⁽²⁾ with DCM and
PLL in Source-Synchronous Mode
XQ5VLX30T
0.46
0.54
0.46
0.57
N/A
ns
XQ5VLX85
0.42
0.68
0.42
0.71
N/A
ns
XQ5VLX110
0.41
0.74
0.41
0.78
N/A
ns
XQ5VLX110T
0.41
0.74
0.41
0.78
N/A
ns
XQ5VLX155T
0.29
1.00
0.33
1.04
N/A
ns
XQ5VLX220T
0.36
1.23
0.38
1.27
N/A
ns
XQ5VLX330T
N/A
0.38
1.46
N/A
ns
XQ5VSX50T
0.43
0.74
0.43
0.77
N/A
ns
XQ5VSX95T
0.41
0.98
0.41
1.02
N/A
ns
XQ5VSX240T
N/A
0.38
1.53
N/A
ns
XQ5VFX70T
0.32
0.78
0.32
0.83
0.32
0.83
ns
XQ5VFX100T
0.35
0.92
0.35
0.96
0.35
0.96
ns
XQ5VFX130T
0.37
1.11
0.41
1.16
N/A
ns
XQ5VFX200T
N/A
0.33
1.46
N/A
ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
2. IFF = Input Flip-Flop
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
71