XQ5VLX30T Datasheet, PDF (70/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 96: Global Clock Setup and Hold with DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard⁽¹⁾
T_PSDCMPLL/
T_PHDCMPLL
No Delay Global Clock and IFF⁽²⁾ with
DCM and PLL in System-Synchronous Mode
XQ5VLX30T
1.89
–0.58
2.06
–0.58
N/A
XQ5VLX85
1.93
–0.51
2.13
–0.51
N/A
XQ5VLX110
1.93
–0.45
2.13
–0.45
N/A
XQ5VLX110T
1.93
–0.45
2.13
–0.45
N/A
XQ5VLX155T
2.31
–0.40
2.55
–0.40
N/A
XQ5VLX220T
2.32
–0.35
2.61
–0.35
N/A
XQ5VLX330T
N/A
2.61
–0.18
N/A
XQ5VSX50T
1.94
–0.45
2.14
–0.45
N/A
XQ5VSX95T
2.51
–0.49
2.53
–0.49
N/A
XQ5VSX240T
N/A
2.70
–0.18
N/A
XQ5VFX70T
2.03
–0.44
2.16
–0.44
2.16
–0.44
XQ5VFX100T
2.51
–0.59
2.66
–0.58
2.66
–0.58
XQ5VFX130T
2.64
–0.51
2.89
–0.51
N/A
XQ5VFX200T
N/A
2.59
–0.30
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
70