XQ5VLX30T Datasheet, PDF (60/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 86: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in Source-Synchronous Mode
T_{ICKOFDCM_0}
Global Clock and OUTFF with DCM
XQ5VLX30T
XQ5VLX85
3.71
4.15
N/A
3.86
4.29
N/A
XQ5VLX110
3.92
4.36
N/A
XQ5VLX110T
3.92
4.36
N/A
XQ5VLX155T
4.18
4.62
N/A
XQ5VLX220T
4.41
4.85
N/A
XQ5VLX330T
N/A
5.04
N/A
XQ5VSX50T
3.91
4.35
N/A
XQ5VSX95T
4.16
4.59
N/A
XQ5VSX240T
N/A
5.11
N/A
XQ5VFX70T
3.96
4.41
4.41
XQ5VFX100T
4.10
4.53
4.53
XQ5VFX130T
4.29
4.74
N/A
XQ5VFX200T
N/A
5.03
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
60