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XQ5VLX30T Datasheet, PDF (47/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
TPL
Program Latency
TPOR
Power-on-Reset
TICCK
CCLK (output) delay
TPROGRAM
Program Pulse Width
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD
DIN Setup/Hold, slave mode
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
TCCO
FMCCK
DOUT
Maximum Frequency, master mode with respect to
nominal CCLK.
FMCCKTOL
Frequency Tolerance, master mode with respect to
nominal CCLK.
FMSCCK
Slave mode external CCLK
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
TSMCSCCK/TSMCCKCS
CS_B Setup/Hold
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
TSMCKCSO
CSO_B clock to out
(330Ω pull-up resistor required)
TSMCO
TSMCKBY
FSMCCK
FRBCCK
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal CCLK
Maximum Readback Frequency with respect to
nominal CCLK
FMCCKTOL
Frequency Tolerance with respect to nominal CCLK
Boundary-Scan Port Timing Specifications
TTAPTCK
TTCKTAP
TTCKTDO
FTCK
FTCKB
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock frequency
Speed Grade
-2I -1I -1M
Units
3
3
3
ms, Max
10
10
10 ms, Min/Max
50
50
50
400 400 400
ns, Min
250 250 250
ns, Min
4.0 4.0 5.0
0.0 0.0 0.0
ns, Min
4.0 4.0 5.0
0.0 0.0 0.0
ns, Min
7.5 7.5 7.5
ns, Max
100 100 100 MHz, Max
±50 ±50 ±50
%
100 100 100
MHz
3.0 3.0 3.0
0.5 0.5 0.5
3.0 3.0 3.0
0.5 0.5 0.5
8.0 8.0 8.0
0.5 0.5 0.5
10
10
10
ns, Min
ns, Min
ns, Min
ns, Min
9.0 9.0 9.0
ns, Max
7.5 7.5 7.5
ns, Max
100 100 100 MHz, Max
60
60
60
MHz, Max
±50 ±50 ±50
%
1.0 1.0 1.0
ns, Min
2.0 2.0 2.0
ns, Min
6
6
6
ns, Max
66
66
66
MHz, Max
66
66
66
MHz, Max
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
47