XQ5VLX30T Datasheet, PDF (39/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Symbol
Description
Setup/Hold
T_{OSDCK_D}/T_{OSCKD_D}
T_{OSDCK_T}/T_{OSCKD_T(1)}
T_{OSDCK_T2}/T_{OSCKD_T2(1)}
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
T_{OSCCK_OCE}/T_{OSCKC_OCE}
OCE input Setup/Hold with respect to CLK
T_{OSCCK_S}
SR (Reset) input Setup with respect to CLKDIV
T_{OSCCK_TCE}/T_{OSCKC_TCE}
TCE input Setup/Hold with respect to CLK
Sequential Delays
T_{OSCKO_OQ}
T_{OSCKO_TQ}
Combinatorial
Clock to out from CLK to OQ
Clock to out from CLK to TQ
T_{OSDO_TTQ}
T_{OSCO_OQ}
T_{OSCO_TQ}
T input to TQ Out
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Notes:
1. T_{OSDCK_T2} and T_{OSCKD_T2} are reported as T_{OSDCK_T/}T_{OSCKD_T} in TRACE report.
Speed Grade
-2I
-1I
-1M
Units
0.24
0.30
0.30
ns
–0.02
–0.02
–0.02
0.34
0.41
0.41
ns
–0.18
–0.18
–0.12
0.24
0.28
0.28
ns
–0.03
–0.03
–0.03
0.19
0.23
0.23
ns
–0.07
–0.07
–0.04
0.58
0.70
0.70
ns
0.23
0.29
0.29
ns
–0.06
–0.06
–0.01
0.60
0.61
0.61
ns
0.62
0.62
0.62
ns
0.70
0.83
0.83
ns
1.82
2.19
2.19
ns
1.89
2.27
2.27
ns
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
39