XQ5VLX30T Datasheet, PDF (65/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 91. Values are expressed in nanoseconds unless otherwise noted.
Table 91: Global Clock Setup and Hold without DCM or PLL
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard⁽¹⁾
T_PSFD/ T_PHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF⁽²⁾ without DCM or PLL
XQ5VLX30T
1.60
–0.35
1.76
–0.35
N/A
XQ5VLX85
1.89
–0.49
2.09
–0.49
N/A
XQ5VLX110
1.88
–0.43
2.09
–0.43
N/A
XQ5VLX110T
1.88
–0.43
2.09
–0.43
N/A
XQ5VLX155T
2.36
–0.50
2.78
–0.49
N/A
XQ5VLX220T
2.57
–0.74
2.86
–0.74
N/A
XQ5VLX330T
N/A
2.86
–0.56
N/A
XQ5VSX50T
1.74
–0.31
1.93
–0.31
N/A
XQ5VSX95T
2.10
–0.44
2.32
–0.44
N/A
XQ5VSX240T
N/A
2.28
0.18
N/A
XQ5VFX70T
2.06
–0.30
2.35
–0.30
2.35
–0.30
XQ5VFX100T
2.38
–0.42
2.66
–0.42
2.66
–0.42
XQ5VFX130T
2.59
–0.54
2.95
–0.54
N/A
XQ5VFX200T
N/A
2.81
–0.43
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
65