XQ5VLX30T Datasheet, PDF (22/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 45: GTX_DUAL Tile User Clock Switching Characteristics
Symbol
Description
Conditions
Device
F_TXOUT TXOUTCLK maximum frequency Internal 20-bit datapath
FXT
Internal 16-bit datapath
FXT
F_RXREC RXRECCLK maximum frequency
FXT
T_RX
RXUSRCLK maximum frequency 2 byte or 4 byte interface
FXT
T_RX2
RXUSRCLK2 maximum frequency 1 byte interface
FXT
2 byte interface
4 byte interface
T_TX
TXUSRCLK maximum frequency 2 byte or 4 byte interface
FXT
T_TX2
TXUSRCLK2 maximum frequency 1 byte interface
FXT
2 byte interface
4 byte interface
Speed Grade
-2I
-1I
-1M
325
212.5
212.5
406.25 265.625 265.625
406.25 265.625 265.625
406.25 265.625 265.625
312.5 235.625 235.625
390.625 265.625 265.625
203.125 132.813 132.813
406.25 265.625 265.625
312.5 235.625 235.625
390.625 265.625 265.625
203.125 132.813 132.813
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max Units
F_GTXTX
T_RTX
T_FTX
T_LLSKEW
V_TXOOBVDPP
T_{TXOOBTRANSITION}
T_J6.5
D_J6.5
T_J5.0
D_J5.0
T_J4.25
D_J4.25
T_J3.75
D_J3.75
T_J3.2
D_J3.2
T_J3.2L
D_J3.2L
T_J2.5
D_J2.5
T_J1.25
D_J1.25
T_J750
D_J750
T_J150
D_J150
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew⁽¹⁾
Electrical idle amplitude
Electrical idle transition time
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter⁽²⁾
Deterministic Jitter⁽²⁾
Total Jitter^{(2, 4)}
Deterministic Jitter^{(2, 4)}
Total Jitter^{(2, 4)}
Deterministic Jitter^{(2, 4)}
20%–80%
80%–20%
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s⁽³⁾
2.5 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
0.15
F_GTXMAX Gb/s
120
ps
120
ps
350
ps
15
mV
75
ns
0.33
UI
0.17
UI
0.33
UI
0.15
UI
0.35⁽⁵⁾
UI
0.14
UI
0.34
UI
0.16
UI
0.20
UI
0.10
UI
0.36
UI
0.16
UI
0.20
UI
0.08
UI
0.15
UI
0.06
UI
0.10
UI
0.03
UI
0.02
UI
0.01
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
3. PLL frequency at 1.6 GHz and OUTDIV = 1.
4. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
5. M-temperature only (0.33 UI for I-temperature)
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
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