XQ5VLX30T Datasheet, PDF (23/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max Units
F_GTXRX
Serial data rate
RX oversampler not enabled
0.75
RX oversampler enabled
0.15
F_GTXMAX
0.75
Gb/s
Gb/s
T_RXELECIDLE
TIme for RXELECIDLE to
respond to loss or
restoration of data
OOBDETECT_THRESHOLD = 110
75
ns
R_XOOBVDPP
OOB detect threshold
peak-to-peak
OOBDETECT_THRESHOLD = 110
55
135
mV
R_XSST
Receiver spread-spectrum
tracking⁽¹⁾
Modulated @ 33 KHz
–5000
0
ppm
R_XRL
Run length (CID)
R_XPPMTOL
Data/REFCLK PPM offset
tolerance
SJ Jitter Tolerance⁽²⁾
JT_SJ_6.5
Sinusoidal Jitter⁽³⁾
JT_SJ_5.0
Sinusoidal Jitter⁽³⁾
JT_SJ_4.25
Sinusoidal Jitter⁽³⁾
JT_SJ_3.75
Sinusoidal Jitter⁽³⁾
JT_SJ_3.2
Sinusoidal Jitter⁽³⁾
JT_SJ_3.2L
Sinusoidal Jitter⁽³⁾
JT_SJ_2.5
Sinusoidal Jitter⁽³⁾
JT_SJ_1.25
Sinusoidal Jitter⁽³⁾
JT_SJ₇₅₀
Sinusoidal Jitter^{(3, 5)}
JT_SJ₁₅₀
Sinusoidal Jitter^{(3, 5)}
SJ Jitter Tolerance with Stressed Eye⁽²⁾
Internal AC capacitor bypassed
CDR 2^nd-order loop disabled
CDR 2^nd-order loop enabled
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s⁽⁴⁾
2.5 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
–200
–2000
0.44
0.44
0.44
0.44
0.45
0.45
0.50
0.50
0.57
0.57
512
UI
200
ppm
2000 ppm
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
JT_TJSE_4.25
Total Jitter with Stressed
Eye⁽⁶⁾
4.25 Gb/s
0.69
UI
JT_SJSE_4.25
Sinusoidal Jitter with
Stressed Eye⁽⁶⁾
4.25 Gb/s
0.1
UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a Bit Error Ratio of 1e^–12.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4. PLL frequency at 1.6 GHz and OUTDIV = 1.
5. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
6. Composite jitter with RX equalizer enabled. DFE disabled.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
23