XQ5VLX30T Datasheet, PDF (64/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in Source-Synchronous Mode
T_{ICKOFDCM0_PLL} Global Clock and OUTFF with DCM and PLL
XQ5VLX30T
XQ5VLX85
3.63
4.06
N/A
3.78
4.20
N/A
XQ5VLX110
3.84
4.27
N/A
XQ5VLX110T
3.84
4.27
N/A
XQ5VLX155T
4.10
4.53
N/A
XQ5VLX220T
4.33
4.76
N/A
XQ5VLX330T
N/A
4.95
N/A
XQ5VSX50T
3.83
4.26
N/A
XQ5VSX95T
4.08
4.50
N/A
XQ5VSX240T
N/A
5.02
N/A
XQ5VFX70T
3.88
4.32
4.32
XQ5VFX100T
4.02
4.44
4.44
XQ5VFX130T
4.21
4.65
N/A
XQ5VFX200T
N/A
4.94
N/A
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS714 (v2.1) July 23, 2010
www.xilinx.com
Product Specification
64