XQ5VLX30T Datasheet, PDF (14/74 Pages) Xilinx, Inc – Virtex-5Q FPGA Data Sheet

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 1
+V
P
N
0
X-Ref Target - Figure 2
+V
Figure 1: Single-Ended Output Voltage Swing
V_SEOUT
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0
DV_PPOUT
DV_PPIN
–V
P–N
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Figure 2: Peak-to-Peak Differential Output Voltage
Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTP
Transceiver User Guide for further details.
Table 29: GTP_DUAL Tile Clock DC Input Specifications⁽¹⁾
Symbol
DC Parameter
V_IDIFF
V_ISE
R_IN
C_EXT
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
Notes:
1. V_MIN = 0V and V_MAX = 1200 mV
Conditions
Min Typ
200 800
100 400
80
105
75
100
Max
2000
1000
130
200
Units
mV
mV
Ω
nF
X-Ref Target - Figure 3
+V
P
N
0
X-Ref Target - Figure 4
+V
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
P–N
V_ISE
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0
V_IDIFF
–V
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS714 (v2.1) July 23, 2010
Product Specification
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