K4N51163QC-ZC Datasheet, PDF (6/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
6.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK, CK
CKE
CS
ODT
RAS, CAS, WE
(L)UDM
BA0 - BA1
A0 - A12
DQ
LDQS,(LDQS)
UDQS,(UDQS)
NC/RFU
V_DDQ
V_SSQ
V_DDL
V_SSL
V_DD
V_SS
V_REF
Type
Input
Input
Input
Function
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi-
tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry
and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selec-
tion on systems with multiple banks. CS is considered part of the command code.
Input
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
Input HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Actove, Read, Write or Precharge command
Input is being applied. BA0 also determines if the mode register or extended mode register is to be accessed dur-
ing a MRS or EMRS cycle.
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank.
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during Mode Register Set commands.
Input/
Output
Data Input/ Output: Bi-directional data bus.
Input/
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data
strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary sig-
nals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. An
EMRS(1) control bit enables or disables all complementary data strobe signals.
No Connect: No internal electrical connection is present.
Supply DQ Power Supply: 1.8V ± 0.1V
Supply DQ Ground
Supply DLL Power Supply: 1.8V ± 0.1V
Supply DLL Ground
Supply Power Supply: 1.8V ± 0.1V
Supply Ground
Supply Reference voltage
-6-
Rev 1.5 Oct. 2005