K4N51163QC-ZC Datasheet, PDF (3/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
8M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM
with Differential Data Strobe
1.0 FEATURES
• 1.8V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• 4 Banks operation
• Posted CAS
• Programmable CAS Letency : 3,4,5
• Programmable Additive Latency : 0, 1, 2, 3 and 4
• Write Latency (WL) = Read Latency (RL) -1
• Burst Legth : 4 and 8 (Interleave/nibble sequential)
• Programmable Sequential/ Interleave Burst Mode
• Bi-directional Differential Data-Strobe
(Single-ended data-strobe is an optional feature)
• Off-chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Refresh and Self Refresh
Average Refesh Period 7.8us at lower then T_CASE 85×C,
3.9us at 85×C < T_CASE < 95 ×C
• Lead Free 84 ball FBGA(RoHS compliant)
2.0 ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
Interface
K4N51163QC-ZC25
400MHz
800Mbps/pin
K4N51163QC-ZC2A
K4N51163QC-ZC33
350MHz
300MHz
700Mbps/pin
600Mbps/pin
SSTL
K4N51163QC-ZC36
275MHz
550Mbps/pin
* K4N51163QC-ZC2A/36 can fully cover previsous K4N51163QF-ZC30/37(667Mbps/533Mbps) product.
* K4N51163QC-GC is the Leaded package part number.
Package
84 Ball FBGA
3.0 GENERAL DESCRIPTION
FOR 8M x 16Bit x 4 Bank gDDR2 SDRAM
The 512Mb gDDR2 SDRAM chip is organized as 8Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed
graphic double-data-rate transfer rates of up to 800Mb/sec/pin for general applications. The chip is designed to comply with the follow-
ing key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD)
impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column,
and bank address information in a RAS/CAS multiplexing style. For example, 512Mb(x16) device receive 13/10/2 addressing. The
512Mb gDDR2 devices operate with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 512Mb gDDR2 devices are avail-
able in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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Rev 1.5 Oct. 2005