K4N51163QC-ZC Datasheet, PDF (10/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
8.9 Input/Output capacitance
Parameter
Input capacitance, CK and CK
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS, DQS
Input/output capacitance delta, DQ, DM, DQS, DQS
- 36
Symbol
Min Max
CCK 1.0 2.0
CDCK x 0.25
CI 1.0 2.0
CDI
x 0.25
CIO 2.5 4.0
CDIO x 0.5
-33
Min Max
1.0 2.0
x 0.25
1.0 2.0
x 0.25
2.5 4.0
x 0.5
- 2A
Min Max
1.0 2.0
x 0.25
1.0 2.0
x 0.25
2.5 3.5
x 0.5
- 25
Units
Min Max
1.0 2.0 pF
x 0.25 pF
1.0 1.75 pF
x 0.25 pF
2.5 3.5 pF
x 0.5 pF
9.0 Electrical Characteristics & AC Timing for - 25/2A/33/36
(0 °C < T_CASE < 95 °C; V_DDQ = 1.8V + 0.1V; V_DD = 1.8V + 0.1V)
9.1 Refresh Parameters
Parameter
Refresh to active/Refresh command time
Average periodic refresh interval
tREFI
Symbol
tRFC
0 °C ≤ T_CASE ≤ 85°C
85 °C < T_CASE ≤ 95°C
512Mb
105
7.8
3.9
9.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS
SPEED
Bin (CL-tRCD-tRP)
Parameter
CAS LATENCY
tCK
tRCD
tRP
tRC
tRAS
-25
5-5-5
min
5
2.5
5
5
21
16
- 2A
5-5-5
min
5
2.86
5
5
18
13
-33
5-5-5
min
5
3.3
5
5
18
13
- 36
4-4-4
min
4
3.6
4
4
15
11
Units
ns
µs
µs
Units
tCK
ns
tCK
tCK
tCK
tCK
- 10 -
Rev 1.5 Oct. 2005