K4N51163QC-ZC Datasheet, PDF (46/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Burst Write followed by Precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied
from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery
time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued
prior to the tWR delay.
Example 1 : Burst Write followed by Precharge: WL = (RL-1) =3, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
DQS
DQs
WL = 3
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
> = t_WR
Precharge A
DIN A₀ DIN A₁ DIN A₂ DIN A₃
Example 2 : Burst Write followed by Precharge: WL = (RL-1) = 4, BL=4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
DQS
DQs
WL = 4
NOP
NOP
NOP
NOP
NOP
Completion of the Burst Write
> = t_WR
Precharge A
DIN A₀ DIN A₁ DIN A₂ DIN A₃
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Rev 1.5 Oct. 2005