K4N51163QC-ZC Datasheet, PDF (42/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
512M gDDR2 SDRAM
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the implementation on
gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally
loaded identically to data bits to insure matched system timing. DM of x16 bit organization is not used during read cycles.
Data Mask Timing
DQS/
DQS
DQ
DM
VIH(ac) V_IH(dc)
V_IL(ac) VIL(dc)
tDS tDH
VIH(ac)_VIH(dc)
V_IL(ac) ^VIL^(dc)
tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min tDQSS
CK
CK
COMMAND
Write
tDQSS
tWR
DQS/DQS
DQ
DM
Case 2 : max tDQSS
DQS/DQS
DQ
DM
tDQSS
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Rev 1.5 Oct. 2005