K4N51163QC-ZC Datasheet, PDF (57/64 Pages) Samsung semiconductor – 512Mbit gDDR2 SDRAM

K4N51163QC-ZC
Refresh command to power down entry
512M gDDR2 SDRAM
T0
T1
T2
T3
T4
T5 T6
T7
T8
T9
T10 T11
CK
CK
CMD
CKE
REF
CKE can go to low one clock after an Auto-refresh command
Active command to power down entry
CMD
CKE
ACT
CKE can go to low one clock after an Active command
Precharge/Precharge all command to power down entry
CMD
CKE
PR or
PRA
CKE can go to low one clock after a Precharge or Precharge all command
MRS/EMRS command to power down entry
CMD
MRS or
EMRS
CKE
tMRD
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously drops “LOW”
during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must sat-
isfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised
“HIGH” again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initialization sequence. DRAM is ready for normal oper-
ation after the initialization sequence. See AC timing parametric table for tDelay specification.
CK#
CK
CKE
tCK
tDelay
Stable clocks
tIS
CKE asynchronously drops low
Clocks can be turned
off after this point
- 57 -
Rev 1.5 Oct. 2005